Synthesis of Regular Logic Bricks for Robust IC Design

With scaling of CMOS technologies to 65nm and below, IC designs are suffering from decreasing yield, increasing variations, and escalating design and manufacturing costs. Regularity in IC design has been recognized as an effective means to combat variability in nanoscale technologies [1]. One methodology to enforce design regularity that produces RET(Resolution Enhancement Technique)-friendly designs is to implement ICs using a small library of regular logic bricks [2]. A regular logic brick is a physical implementation of logic function(s) created from a small set of logic primitives that are mapped onto a regular layout fabric. In this project, we propose a methodology for the design and synthesis of such logic bricks. Since logic bricks are comprised of a limited set of logic primitives for manufacturability reasons, we propose a primitive-based direct mapping approach for generating optimized bricks that, in contrast to classical synthesis approaches, can provide direct control of implementation structures at abstract functional level based on the detection of natural decompositions that exist in the function.